use rust_hdl::core::prelude::*;

pub const CLOCK_SPEED_12MHZ: u64 = 12_000_000;

#[derive(LogicBlock)]
pub struct InternalClock {
    pub clk: Signal<Out, Clock>,
}

impl InternalClock {
    pub fn new() -> Self {
        let clk = Signal::<Out, _>::default();
        Self { clk }
    }
}

impl Logic for InternalClock {
    fn update(&mut self) {}

    fn connect(&mut self) {
        self.clk.connect();
    }

    fn hdl(&self) -> Verilog {
        Verilog::Wrapper(Wrapper {
            code: "SB_HFOSC hfosc(.CLKHFPU(1'b1), .CLKHFEN(1'b1), .CLKHF(clk));".into(),
            cores: r#"
                module SB_HFOSC(CLKHFPU, CLKHFEN, CLKHF);
                    input CLKHFPU;
                    input CLKHFEN;
                    output CLKHF;
                endmodule"#
                .into(),
        })
    }
}

pub fn leds() -> Signal<Out, Bits<3>> {
    let mut x = Signal::<Out, _>::default();
    for (ndx, uname) in ["39", "40", "41"].iter().enumerate() {
        x.add_location(ndx, uname);
    }
    x
}